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12 - bit, 20/40/65 msps 3 v a/d converter data sheet ad9235 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no r e- sponsibility is assumed by analog devices for its use, n or for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trade marks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features single 3 v supply operation (2.7 v to 3.6 v) snr = 70 dbc to nyquist at 65 msps sfdr = 85 dbc to nyquist at 65 msps low power: 300 mw at 65 msps differential input with 500 mhz bandwidth on - chip reference and sha dnl = 0.4 lsb flexible analog inp ut: 1 v p - p to 2 v p - p range offset binary or twos complement data format clock duty cycle stabilizer applications ultrasound equipment if sampling in communications receivers is - 95, cdma - one, imt - 2000 battery - powered instruments hand - held scopemeters low cost digital oscilloscopes functional block diagram sha vin+ vin? drvdd 8-stage 1 1/2-bit pipeline clk pdwn mode clock duty cycle stabilizer mode select dgnd otr d11 d0 avdd mdac1 correction logic output buffers ref select agnd 0.5v vref sense ad9235 02461-001 reft refb a/d a/d 4 16 12 3 figure 1. general description the ad9235 is a family of monolithic, single 3 v supply, 12 - bit, 20/40/65 msps analog - to - digital converters (adcs). this fa m ily features a hig h performance sample - and - hold amplifier (sha) and voltage reference. the ad9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12 - bit accuracy at 20/40/65 msps data rates and guarantee no missing codes o ver the full operating te m perature range. the wide bandwidth, truly differential sha allows a variety of user - selectable input ranges and offsets including single - ended applications. it is suitable for multiplexed systems that switch full - scale voltage le vels in successive channels and for sampling single - channel inputs at frequencies well beyond the nyquist rate . combined with power and cost savings over previously avail a ble adcs, the ad9235 is suitable for applications in communic a- tions, imaging, and med ical ultrasound. a single - ended clock input is used to control all internal co n version cycles. a duty cycle stabilizer (dcs) compensates for wide variations in the clock duty cycle while maintaining excellent overall adc performance. the digital output da ta is pr e sented in straight binary or twos complement formats. an out - of - range (otr) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. fabricated on an advanced cmos process, the ad9235 is avai l- able in a 28 - lead tssop and a 32 - lead lfcsp and is specified over the industrial temperature range ( C 40c to +85c). product highlights 1. the ad9235 operates from a single 3 v power supply and features a separate digital output driver supply to acco mmo- date 2.5 v and 3.3 v logic families. 2. operating at 65 msps, the ad9235 consumes a low 300 m w. 3. the patented sha input maintains excellent performance for input frequencies up to 100 mhz and can be configured for single - ended or differential operation. 4. the ad9235 pinout is similar to the ad9214 - 65, a 10 - bit, 65 msps adc. this allows a simplified upgrade path from 10 bits to 12 bits for 65 msps systems. 5. the clock dcs maintains overall adc performance over a wide range of clock pulse widths. 6. the otr output bi t indicates when the signal is beyond the selected input range.
ad9235 data sheet rev. d | page 2 of 40 table of contents specifications ..................................................................................... 3 dc specifications ......................................................................... 3 digital specifications ................................................................... 4 switching specifications .............................................................. 4 ac specifications .......................................................................... 5 absolute maximum ratings ............................................................ 7 explanation of test levels ........................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 definitions of specifications ........................................................... 9 equ ivalent circuits ......................................................................... 10 typical performance characteristics ........................................... 11 applying the ad9235 .................................................................... 15 theory of operation .................................................................. 15 analog input ............................................................................... 15 clock input considerations ...................................................... 16 power dissipation and standby mode .................................... 17 digital outputs ........................................................................... 18 voltage reference ....................................................................... 18 operational mode selection ..................................................... 19 tssop evaluation board .......................................................... 19 lfcsp evaluation board ........................................................... 20 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 37 revision history 1 0 /12 rev. c to rev. d changes to figure 4 and table 6 ................................ ................................ 8 updated outline dimensions (changed cp - 32 - 2 to cp - 32- 7 ) ..... 36 changes to ordering guide .......................................................... 37 10 /04 data sheet changed from rev. b to rev. c changes to format ............................................................. universal changes to specifications ................................................................. 3 changes to the ordering guide .................................................... 3 7 5/03 data sheet changed from rev. a to rev. b ad ded cp - 32 package (lfcsp) ........................................ universal changes to several pin names .......................................... universal changes to features ........................................................................... 1 changes to product description ..................................................... 1 changes to product highlights ........................................................ 1 changes to specifications ................................................................. 2 replaced figure 1 .............................................................................. 3 changes to absolute maximum ratings ........................................ 5 changes to ordering guide ............................................................. 5 changes to pin function descriptions ........................................... 6 new definitions of specifications section ..................................... 7 changes to tpcs 1 to 12 .................................................................. 9 changes to theory of operation section ..................................... 13 changes to analog input section .................................................. 13 changes to single - ended input configuration sectio n ............. 14 replaced figure 8 ............................................................................ 14 changes to clock input considerations section ........................ 14 changes to table i ........................................................................... 15 changes to power dissipation and standby mode section ....... 15 changes to digital outputs section .............................................. 15 changes to timing section ............................................................ 15 changes to figure 13 ....................................................................... 16 changes to figures 16 to 26 ........................................................... 17 added lfcsp evaluation board section ..................................... 17 inserted figures 27 to 35 ................................................................ 25 added table iii ................................................................................ 30 updated outline dimensions ........................................................ 31 8/02 data sheet changed from rev. 0 to rev. a updated ru - 28 package ................................................................ 24
data sheet ad9235 rev. d | page 3 of 40 specifications dc specifications av d d = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference, t min to t max , unless otherwise noted. table 1 . parameter temp test level ad9235bru/bcp - 20 ad9235bru/bcp - 40 ad9235bru/bcp - 65 unit min ty p max min typ max min typ max resolution full vi 12 12 12 bits accuracy no missing codes guaranteed full vi 12 12 12 bits offset error full vi 0.30 1.20 0.50 1.20 0.50 1.20 % fsr gain error 1 full vi 0.30 2.40 0 .50 2.50 0.50 2.60 % fsr differential nonlinearity (dnl) 2 full iv 0.35 0.65 0.35 0.75 0.40 0.80 lsb 25c i 0.35 0.35 0.35 lsb integral nonlinearity (inl) 2 full iv 0.45 0.80 0.50 0.90 0.70 1.30 lsb 25c i 0.40 0.40 0.45 lsb temperature drift offset error full v 2 2 3 ppm/c gain error full v 12 12 12 ppm/c internal voltage reference output voltage error (1 v mode) full vi 5 35 5 35 5 35 mv load regulation @ 1.0 ma full v 0.8 0.8 0.8 mv output voltage error (0.5 v mode) full v 2.5 2.5 2.5 mv load regulation @ 0.5 ma full v 0.1 0.1 0.1 mv input referred noise vref = 0.5 v 25c v 0.54 0.5 4 0.54 lsb rms vref = 1.0 v 25c v 0.27 0.27 0.27 lsb rms analog input input span, vref = 0.5 v full iv 1 1 1 v p -p input span, vref = 1.0 v full iv 2 2 2 v p - p input capacitance 3 full v 7 7 7 pf reference input resistance full v 7 7 7 k? power supplies supply voltages avdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd full iv 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 v supply current iavdd 2 full v 30 55 100 ma idrvdd 2 full v 2 5 7 ma psrr full v 0.01 0.01 0.01 % fsr power consumption dc input 4 full v 90 165 300 mw sine wave input 2 full vi 95 110 180 205 320 350 mw standby power 5 full v 1.0 1.0 1.0 mw 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate, f in = 2.4 mhz, full - scale sin e wave, with approximately 5 pf loading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and agnd. refer to figure 5 for the equivalent analog input structure. 4 measure d with dc input at maximum clock rate. 5 standby power is measured with a dc input, the clk pin inactive (i.e., set to avdd or agnd).
ad9235 data sheet rev. d | page 4 of 40 digital specificatio ns table 2 . parameter temp test level ad9235bru/bcp - 20 ad9235bru/bcp - 40 ad9235bru/bcp - 65 unit min typ max min typ max min typ max logic inputs high level input voltage full iv 2.0 2.0 2.0 v low level input voltage full iv 0.8 0.8 0.8 v high level input current full iv C 10 +10 C 10 +10 C 10 +10 a low level input current full iv C 10 +10 C 10 +10 C 10 +10 a input ca pacitance full v 2 2 2 pf logic outputs 1 drvdd = 3.3 v high - level output voltage full iv 3.29 3.29 3.29 v (ioh = 50 a) high - level output voltage full iv 3.25 3.25 3.25 v (ioh = 0.5 ma) low - level output voltage full iv 0.2 0.2 0.2 v (iol = 1.6 ma) low - level output voltage full iv 0.05 0.05 0.05 v (iol = 50 a) drvdd = 2.5 v high - level output voltage full iv 2.49 2.49 2.49 v (i oh = 50 a) high - level output voltage full iv 2.45 2.45 2.45 v (ioh = 0.5 ma) low - level output voltage full iv 0.2 0.2 0.2 v (iol = 1.6 ma) low - level output voltage full iv 0.05 0.05 0.05 v (iol = 50 a) 1 output voltage levels measured with 5 pf load on each output. switching specificat ions table 3 . parameter temp test level ad9235bru/bcp - 20 ad9235bru/bcp - 40 ad9235bru/bcp - 65 unit min typ max min typ max min typ max clock input parameters maximum conversi on rate full vi 20 40 65 msps minimum conversion rate full v 1 1 1 msps clk period full v 50.0 25.0 15.4 ns clk pulse - width high 1 full v 15.0 8.8 6.2 ns clk pulse - width low 1 full v 15.0 8.8 6. 2 ns data output parameters output delay 2 (t pd ) full v 3.5 3.5 3.5 ns pipeline delay (latency) full v 7 7 7 cycles aperture delay (t a ) full v 1.0 1.0 1.0 ns aperture uncertainty jitter (t j ) full v 0.5 0.5 0.5 ps rms wake - up time 3 full v 3.0 3.0 3.0 ms out -of - range recovery time full v 1 1 2 cycles 1 for the ad9235 - 65 model only, with duty cycle stabilizer enabled. dcs function not applicable for - 20 and - 40 models. 2 output delay is measured from clk 50% transition to data 50% transition, with 5 pf load on each output. 3 wake - up time is dependent on value of decoupling capacitors; typical values shown with 0.1 f and 10 f capacitors on reft and refb.
data sheet ad9235 rev. d | page 5 of 40 t a t pd = 6.0ns max 2.0ns min n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n analog input clk data out n ? 1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 02461-002 figure 2 . timing diagram ac specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p - p differential input, a in = C 0.5 dbfs, 1.0 v internal reference, t min to t max , unless otherwise noted. table 4 . ad9235bru/bcp - 20 ad9235bru/bcp - 40 ad9235bru/bcp - 65 parameter temp test level min typ max min typ max min typ max unit signal -to - noise r atio f input = 2.4 mhz 25c v 70.8 70.6 70.5 dbc f input = 9.7 mhz full iv 70.0 70.4 dbc 25c i 70.6 dbc f input = 19.6 mhz full iv 69.9 70.3 dbc 25c i 70.4 dbc f input = 32.5 mhz full iv 68.7 6 9.7 dbc 25c i 70.1 dbc f input = 100 mhz 25c v 68.7 68.5 68.3 dbc signal -to - noise ratio and distortion f input = 2.4 mhz 25c v 70.6 70.5 70.4 dbc f input = 9.7 mhz full iv 69.9 70.3 dbc 25c i 70.5 d bc f input = 19.6 mhz full iv 69.7 70.2 dbc 25c i 70.3 dbc f input = 32.5 mhz full iv 68.3 69.5 dbc 25c i 69.9 dbc f input = 100 mhz 25c v 68.6 68.3 67.8 dbc total harmonic distortion f input = 2.4 m hz 25c v C 88.0 C 89.0 C 87.5 dbc f input = 9.7 mhz full iv C 86.0 C 79.0 dbc 25c i C 87.4 dbc f input = 19.6 mhz full iv C 85.5 C 79.0 dbc 25c i C 86.0 dbc f input = 32.5 mhz full iv C 81.8 C 74.0 dbc 25c i C 82.0 dbc f input = 100 mhz 25c v C 84.0 C 82.5 C 78.0 dbc worst harmonic (second or third) f input = 9.7 mhz full iv C 90.0 C 80.0 dbc f input = 19.6 mhz full iv C 90.0 C 80.0 dbc f input = 32.5 mhz full iv C 83.5 C 74.0 dbc
ad9235 data sheet rev. d | page 6 of 40 ad9235bru/bcp - 20 ad9235bru/bcp - 40 ad9235bru/bcp - 65 parameter temp test level min typ max min typ max min typ max unit spurious - free dynamic range f input = 2.4 mhz 25c v 92.0 92.0 92.0 dbc f input = 9.7 mhz full iv 80.0 88.5 dbc 25c i 91.0 dbc f input = 19.6 mhz full iv 80.0 89.0 dbc 25c i 90.0 dbc f input = 32.5 mhz full iv 74.0 83.0 dbc 25c i 85.0 dbc f input = 100 mhz 25c v 84.0 85.0 80.5 dbc
data sheet ad9235 rev. d | page 7 of 40 absolute maximum rat ings table 5 . pin name with r e spect to min max unit electrical avdd agnd C 0.3 +3.9 v drvdd dgnd C 0.3 +3.9 v agnd dgnd C 0.3 +0.3 v avdd drvdd C 3.9 +3.9 v digital ou t puts dgnd C 0.3 drvdd + 0.3 v clk, mode agnd C 0.3 avdd + 0.3 v vin+, vin C agnd C 0.3 avdd + 0.3 v vref agnd C 0.3 avdd + 0.3 v sense agnd C 0.3 avdd + 0.3 v r efb, reft agnd C 0.3 avdd + 0.3 v pdwn agnd C 0.3 avdd + 0.3 v environmental 1 operating temperature C 40 +85 c junction temperature 150 c lead temperature (10 sec) 300 c storage temperature C 65 +150 c 1 typical thermal impedances (28 - lead tssop), ja = 67.7c/w; (32 - lead lfcsp), ja = 32.5c/w, jc = 32.71c/w. these measurements were taken on a 4 - layer board in still air, in accordance with eia/jesd51 - 1. absolute maximum ratings are limiting val ues to be applied individually and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily i m plied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliabili ty. explanation of test levels test levels description i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characteriz a- tion testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by d e- sign and characterization testing for industrial te m- perature range; 100% production tested at temper a- ture extremes for military devices. esd caution esd (electrost atic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage ma y occur on devices subjected to high energy ele c- trostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9235 data sheet rev. d | page 8 of 40 pin configurations a nd function descript ions 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 28 27 26 25 24 23 22 21 20 1 9 1 8 1 7 1 6 1 5 ad9235 top view (not to scale) mode sense vref avdd reft refb otr d10 d9 d8 d7 dgnd drvdd agnd vin+ vin ? pdwn avdd agnd d6 d5 d4 d0 (lsb) clk d1 d2 d3 d11 (msb) 02461-003 figure 3 . 28 - lead tssop pin configuration 02461-004 notes 1. dnc = do not connect. 2. it is recommended that the exposed paddle be soldered to the ground plane. avdd refb reft avdd agnd vin+ vin? agnd d8 d9 d10 d11 (msb) otr mode sense vref d7 dgnd drvdd d6 d5 d4 d3 d2 d1 d0 (lsb) dnc dnc pdwn dnc clk dnc ad9235 top view (not to scale) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 figure 4 . 32 - lead lfcsp pin configuration table 6 . pin function descriptions pin no. 28- lead tssop pin no. 32- lead lfcsp mnemonic description 1 21 otr out -of - range indicator. 2 22 mode data format and clock duty cycle stabilizer (dcs) mode selection. 3 23 sense reference mode selection. 4 24 vref voltage reference input/output. 5 25 refb differential reference (?). 6 26 reft differential reference (+). 7, 12 27, 32 avdd analog power supply. 8, 11 28, 31 agnd analog ground. 9 29 vin+ analog input pin (+). 10 30 vin C analog input pin (?). 13 2 clk clock input pin. 14 4 pdwn power - down function selection (active high). 15 to 22, 25 to 28 7 to 14, 17 to 20 d0 (lsb) to d11 (msb) data output bits. 23 15 dgnd digital output ground. 24 16 drvdd digital output driver supply. must be decoupled to dgnd with a minimum. 0.1 f capacitor. recommended decoupling is 0.1 f in parallel with 10 f. 1, 3, 5, 6 dnc do not connect. ep epad exposed pad. it is recommended that the exposed paddle be soldered to the ground plane . there is an increased reliability of the solder joints and max i- mum thermal capability of the package is achieved with exposed paddle so ldered to the customer board.
data sheet ad9235 rev. d | page 9 of 40 definitions of speci fications analog bandwidth (full power bandwidth) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay (t a ) the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture jitter (t j ) the sample - to - sample variation in aperture delay. integral nonlinearity (inl) the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1 ? lsbs beyond the last code transition. the deviat ion is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12 - bit resolution indicates that all 4096 codes must be present over all operating ranges. offset error the major carry transition should occur for an analog value ? lsb below vin+ = vin C . offset error is defined as the devi a tion of t he actual transition from that point. gain error the first code transition should occur at an analog value ? lsb above negative full scale. the last transition should occur at an analog value 1 ? lsb below the positive full scale. gain error is the deviati on of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for offset error and gain error specifies the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection ratio the change in full scale from the value with the supply at the minimum limit to the value with the supply at its max i mum limit. total harmonic distortion (thd) 1 the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. 1 ac specifications may be reported in dbc (degrades as signal levels are lo w ered) or in dbfs (always related back to converter full scale). signal -to - noise and distortion (sinad) 1 the ratio of the rms signal amplitude (set 0.5 db below full scale) to the rms value of the sum of a ll other spectral comp o- nents below the nyquist frequency, including harmonics but excluding dc. effective number of bits (enob) the enob for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad using t he following formula n = ( sinad ? 1.76)/6.02 signal -to - noise ratio (snr) 1 the ratio of the rms signal amplitude (set at 0.5 db below full scale) to the rms value of the sum of all other spectral comp o- nents below the nyquist frequency, excluding the first six ha r monics and dc. spurious - free dynamic range (sfdr) 1 the difference in db between the rms amplitude of the input signal and the peak spurious signal. two - ton e sf dr 1 the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. clock pulse width and duty cycle pulse - width high is the minimum amount of time that th e clock pulse should be left in the logic 1 state to achieve rated pe r formance. pulse - width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these spec i fications define an acceptable clock duty cycle. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay (t pd ) t he delay between the clock logic threshold and the time when all bits are within valid logic levels. out -of - range recovery time the time it takes for the adc to reacquire the analog input after a transition from 10% above positive full scale to 10% above n egative full scale, or from 10% below negative full scale to 10% below positive full scale.
ad9235 data sheet rev. d | page 10 of 40 equivalent circuits avdd vin+, vin? 02461-005 figure 5 . equivalent analog input circuit avdd mode 20k ? 02461-006 figure 6 . equivalent mode input circuit d11 ?d0, otr drvdd 02461-007 figure 7 . equivalent digital output circuit 02461-008 clk, pdwn avdd figure 8 . equivalent digital input circuit
data sheet ad9235 rev. d | page 11 of 40 typical performance characteristics avdd = 3.0 v, drvdd = 2.5 v, f sample = 65 msps with dcs disabled, t a = 25 c, 2 v differential input, a in = ?0.5 dbfs, vref = 1.0 v, unless otherwise noted. 02461-009 frequency (mhz) 32.5 0 6.5 13.0 19.5 26.0 magnitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 70.3dbc sinad = 70.2dbc enob = 11.4 bits thd = ? 86.3dbc sfdr = 89.9dbc figure 9 . single tone 8k fft with f in = 10 mhz 02461-010 frequency (mhz) 91.0 65.0 71.5 78.0 84.5 magnitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 69.4dbc sinad = 69.1dbc enob = 11.2 bits thd = ?81.0dbc sfdr = 83.8dbc figure 10 . single tone 8k fft with f in = 70 mhz 02461-011 frequency (mhz) 130.0 97.5 104.0 110.5 117.0 123.5 magnitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 68.5dbc sinad = 66.5dbc enob = 10.8 bits thd = ?71.0dbc sfdr = 71.2dbc figure 11 . single tone 8 k fft with f in = 100 mhz 02461-012 sample rate (msps) 65 40 45 50 55 60 snr/sfdr (dbc) 100 95 90 80 70 60 85 75 65 55 50 sfdr (2v diff) snr (2v se) snr (2v diff) sfdr (2v se) figure 12 . ad9235 - 65: single tone snr/sfdr vs. f clk with f in = nyquist (32.5 mhz) 02461-013 sample rate (msps) 40 20 25 30 35 snr/sfdr (dbc) 100 95 90 85 80 75 70 65 60 55 50 snr (2v se) sfdr (2v diff) snr (2v diff) sfdr (2v se) figure 13 . ad9235 - 40: single tone snr/sfdr vs. f clk with f in = nyquist (20 mhz) 02461-014 sample rate (msps) 20 0 5 10 15 snr/sfdr (dbc) 100 90 95 85 80 75 65 70 55 60 50 sfdr (2v diff) snr (2v diff) sfdr (2v se) snr (2v se) figure 14 . ad9235 - 20: single tone snr/sfdr vs. f clk with f in = nyquist (10 mhz)
ad9235 data sheet rev. d | page 12 of 40 02461-015 a in (dbfs) 0 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 snr/sfdr (dbfs and dbc) 100 90 80 70 60 50 40 sfdr single-ended (dbfs) sfdr differential (dbc) snr differential (dbfs) sfdr single-ended (dbc) snr differential (dbc) snr single-ended (dbc) sfdr differential (dbfs) snr single-ended (dbfs) figure 15 . ad9235 - 65: single tone snr/sfdr vs. a in with f in = nyquist (32.5 mhz) 02461-016 a in (dbfs) 0 ?30 ?25 ?20 ?15 ?10 ?5 snr/sfdr (dbfs and dbc) 100 90 80 70 60 50 40 sfdr single-ended (dbfs) snr differential (dbc) snr single-ended (dbc) snr differential (dbfs) snr single-ended (dbfs) sfdr single-ended (dbc) sfdr differential (dbc) sfdr differential (dbfs) figure 16 . ad9235 - 40: single tone snr/sfdr vs. a in with f in = nyquist (20 mhz) 02461-017 a in (dbfs) 0 ?30 ?25 ?20 ?15 ?10 ?5 snr/sfdr (dbfs and dbc) 100 90 80 70 60 50 40 snr differential(dbc) snr single-ended (dbc) snr differential (dbfs) snr single-ended (dbfs) sfdr differential (dbc) sfdr single-ended (dbfs) sfdr differential (dbfs) sfdr single-ended(dbc) figure 17 . ad9235 - 20: single tone snr/sfdr vs. a in with f in = nyquist (10 mhz) 02461-018 input frequency (mhz) 125 0 25 50 75 100 snr/sfdr (dbc) 95 90 85 80 75 70 65 snr sfdr figure 18 . ad9235 - 65: snr/sfdr vs. f in 02461-019 input frequency (mhz) 125 0 25 50 75 100 snr/sfdr (dbc) 95 90 85 80 75 70 65 snr sfdr figure 19 . ad9235 - 40: snr/sfdr vs. f in 02461-020 input frequency (mhz) 125 0 25 50 75 100 snr/sfdr (dbc) 95 90 85 80 75 70 65 snr sfdr figure 20 . ad9235 - 20: snr/sfdr vs. f in
data sheet ad9235 rev. d | page 13 of 40 02461-021 frequency (mhz) 65.0 32.5 39.0 45.5 52.0 58.5 magnitude (dbfs) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 snr = 64.6dbfs sfdr = 81.6dbfs figure 21 . dual tone 8k fft with f in1 = 45 mhz and f in2 = 46 mhz 02461-022 frequency (mhz) 97.5 65.0 71.5 78.0 84.5 91.0 magnitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 64.3dbfs sfdr = 81.1dbfs figure 22 . dual tone 8k fft with f in1 = 69 mhz and f in2 = 70 mhz 02461-023 frequency (mhz) 162.0 130.0 136.5 143.0 149.5 156.0 magnitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?120 snr = 62.5dbfs sfdr = 75.6dbfs figure 23 . dual tone 8k fft with f in1 = 144 mhz and f in2 = 145 mhz 02461-024 a in (dbfs) ?6 ?24 ?21 ?18 ?15 ?12 ?9 snr/sfdr (dbfs) 95 90 85 80 75 70 65 60 1v snr 1v sfdr 2v snr 2v sfdr figure 24 . dual tone snr/sfdr vs. a in with f in1 = 45 mhz and f in2 = 46 mhz 02461-025 a in (dbfs) ?6 ?24 ?21 ?18 ?15 ?12 ?9 snr/sfdr (dbfs) 95 90 85 80 75 70 65 60 1v snr 1v sfdr 2v snr 2v sfdr fi gure 25 . dual tone snr/sfdr vs. a in with f in1 = 69 mhz and f in2 = 70 mhz 02461-026 a in (dbfs) ?6 ?24 ?21 ?18 ?15 ?12 ?9 snr/sfdr (dbfs) 95 90 85 80 75 70 65 60 1v snr 1v sfdr 2v snr 2v sfdr figure 26 . dual tone snr/sfdr vs. a in with f in1 = 144 mhz and f in2 = 145 mhz
ad9235 data sheet rev. d | page 14 of 40 02461-027 sample rate (msps) 60 0 10 20 30 40 50 enob (bits) 9.7 12.2 11.7 11.2 10.7 10.2 sinad (dbc) 75 72 69 66 63 60 ad9235-65: 1v sinad ad9235-40: 2v sinad ad9235-65: 2v sinad ad9235-20: 2v sinad ad9235-20: 1v sinad ad9235-40: 1v sinad figure 27 . sinad vs. f c lk with f in = nyquist 02461-028 duty cycle (%) 65 35 40 45 50 55 60 sinad/sfdr (dbc) 90 80 70 60 50 40 30 sinad: dcs off sfdr: dcs off sfdr: dcs on sinad: dcs on figure 28 . sinad/sfdr vs. clock duty cycle 02461-029 sample rate (msps) 80 ? 40 ? 30 ? 20 ? 10 0 10 20 30 40 50 60 70 sinad/sfdr (dbc) 90 85 80 75 70 60 55 65 50 sinad 2v diff sinad 1v diff sfdr 1v diff sfdr 2v diff figure 29 . sinad/sfdr vs. temperature with f in = 32.5 mhz 02461-030 temperature ( c ) 80 ? 40 0 ? 20 20 40 60 gain draft (ppm/ c) 20 15 10 5 0 ? 5 ? 10 ? 15 ? 20 figure 30 . a/d gain vs. temperature using an e xternal reference 02461-031 code 4000 0 500 1000 1500 2000 2500 3000 3500 inl (lsb) 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 figure 31 . typical inl 02461-032 code 4000 0 500 1000 1500 2000 2500 3000 3500 dnl (lsb) 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 figure 32 . typical dnl
data sheet ad9235 rev. d | page 15 of 40 applying the ad9235 theory of operation the ad9235 architecture consists of a front end sha followed by a pipelined switched capac itor adc. the pipelined adc is divided into three sections, consisting of a 4 - bit first stage fo l lowed by eight 1.5 - bit stages and a final 3 - bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quanti zed outputs from each stage are combined into a final 12 - bit result in the digital correction lo g- ic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on pr e ceding samples. sampling occu rs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference betwee n the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a d ifferential sha that can be ac - or dc - coupled in differential or single - ended modes. the output - staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate suppl y, allowing adjustment of the output voltage swing. during power - down, the output buffers go into a high impedance state. analog input the analog input to the ad9235 is a differential switched capacitor sha that has been designed for optimum perfo r- mance w hile processing a differential input signal. the sha input can support a wide common - mode range and maintain excellent performance, as shown in figure 34 . an input co m mon - mode voltage of mi dsupply minimizes signal - depende nt error s and pr o vides optimum performance. referring to figure 33 , the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed ac ross the inputs to provide dynamic charging currents. this passive network creates a low - pass filter at the adcs input; therefore, the precise values are depend e nt upon the application. in if undersampling applications, any shunt capac i tors should be r emoved. in combination with the driving source impedance, they would limit the input bandwidth. for best dynamic performance, the source impe d ances driving vin+ and vin C should be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. vin+ vin ? c par c par 5pf 5pf t t 02461-033 h t t h figure 33 . switched - capacitor sha input an internal differential reference buffer creates positive and negative reference voltages, reft and refb, respectively, that define th e span of the adc core. the output common mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as: reft = ?( av d d + vref ) refb = ?( av d d ? vref ) span = 2 ( reft ? refb ) = 2 vref it can be seen from the equa tions above that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. 02461-034 common-mode level (v) 3.0 0 0.5 1.0 1.5 2.0 2.5 thd (dbc) ? 50 ? 90 ? 75 ? 80 ? 85 ? 55 ? 60 ? 65 ? 70 snr (dbc) 90 85 80 75 70 65 60 55 50 snr 35mhz 2v diff thd 35mhz 2v diff thd 2.5mhz 2v diff snr 2.5mhz 2v diff figure 34 . ad9235 - 65: snr, thd vs. common - mode level
ad9235 data sheet rev. d | page 16 of 40 the intern al voltage reference can be pin - strapped to fixed values of 0.5 v or 1.0 v, or adjusted within the same range as discussed in the internal reference connection section. max i- mum snr performance is achieved with the ad9235 set to th e largest input span of 2 v p - p. the relative snr degradation is 3 db when changing from 2 v p - p mode to 1 v p - p mode. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference vol t- age. the minimu m and maximum common - mode input levels are defined as: vcm min = vref /2 vcm max = ( av d d + vref )/2 the minimum common - mode input level allows the ad9235 to accommodate ground - referenced inputs. although optimum performance is achieved with a differential inpu t, a single - ended source may be driven into vin+ or vin C . in this configuration, one input accepts the signal, while the o p posite input should be set to midscale by connecting it to an appropriate reference. for example, a 2 v p - p signal may be applied to vin+ while a 1 v reference is applied to vin C . the ad9235 then accepts an input signal varying between 2 v and 0 v. in the single - ended configuration, distortion perfor m ance may degrade significantly as compared to the differential case. however, the effec t is less noticeable at lower input fr e quencies and in the lower speed grade models (ad9235 - 40 and ad9235 - 20). differential input configurations as previously detailed, optimum performance is achieved while driving the ad9235 in a differential input config uration. for baseband applications, the ad8138 differential driver pr o vides excellent performance and a flexible interface to the adc. the output common - mode voltage of the ad8138 is easily set to avdd/2, and the driver can be configured in a sallen - key fi lter topology to provide band limiting of the input signal. ad9235 vin+ vin ? avdd 1vp-p 49.9 ? 523 ? 1k ? 1k ? 0.1 f 22 ? 22 ? 15pf 15pf 499 ? 499 ? 499 ? agnd 02461-035 ad8138 figure 35 . differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers is not adequat e to achieve the true performance of the ad9235. this is especially true in if undersampling applications where freque n cies in the 70 mhz to 100 mhz range are being sampled. for th e se applications, differential transformer coupling is the recommended inp ut co n figuration, as shown in figure 36. 02461-036 ad9235 vin+ vin? avdd 49.9? 22? 22? 15pf 15pf agnd 1k? 1k? 0.1f 2vp-p figure 36 . differential transformer - coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies b e low a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single - ended input configuration a single - ended input may provide adequate performance in cost - sensitive applications. in this configura tion, there is degr a- dation in sfdr and in distortion performance due to the large input common - mode swing. however, if the source i m pedances on each input are matched, there should be little effect on snr performance. figure 37 de tails a typical single - ended input configuration. 02461-037 ad9235 vin+ vin? avdd 49.9? 22? 22? 15pf 15pf agnd 1k? 1k? 1k? 1k? 2vp-p 0.33f 0.1f 10f figure 37 . single - ended input configuration clock input consider ations typical high speed adcs use both clock edges to generate a variety of internal timing signals, and as a resu lt, may be sens i- tive to clock duty cycle. commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance cha r- acteristics. the ad9235 contains a clock duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an i nternal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the perfo r- mance of the ad9235. as shown in figure 30 , noise and disto r- tion performance are nearly flat over a 30% range of duty cycle. the duty cycle stabilizer uses a delay - locked loop (dll) to create the nonsampling edge. as a result, any changes to the sa m pling frequency require approximately 100 clock cycles to allow the dll to acquire and lock to the new ra te.
data sheet ad9235 rev. d | page 17 of 40 high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full - scale input frequency (f input ) due only to aperture jitter (t j ) can be calculated by snr degradation = ? 20 log 10 [2 f input t j ] in the equation, the rms aperture jitter, t j , represents the root - sum square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. u n dersampling applications are par ticularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9235. power supplies for clock drivers should be separated from the adc output driver supplies to avoi d modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original cl ock at the last step. power dissipation an d standby mode as shown in figure 38 , the power dissipated by the ad9235 is proportional to its sample rate. the digital power dissipation does not vary substantially between the three spee d grades b e cause it is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current can be calculated as i drvdd = v drvdd c load f clk n where n is the number of output bits, 12 in the case of t he ad9235. this maximum current occurs when every output bit switches on every clock cycle, i.e., a full - scale square wave at the nyquist frequency, f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is determined by the encode rate and the characte r istics of the analog input signal. 02461-038 sample rate (msps) 60 0 10 20 30 40 50 total power (mw) 325 300 275 250 225 200 175 150 125 100 75 50 ad9235-20 ad9235-40 ad9235-65 figure 38 . total power vs. sample rate with f in = 10 mhz for the ad9235 - 20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. digital power consumption can be minimized by reducing the capac i- tive load presented to the output drivers. the data in figure 38 was taken with a 5 pf load on each output driver. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. by asserting the pdwn pin high, the ad9235 is placed in standby mode. in this state, the adc typically dissipates 1 mw if the clk and analog inputs are static. during standby, the ou t put drivers are placed in a high impedance state. reasserting the pdwn pin low returns the ad92 35 into its normal oper a tional mode. low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering standby mode and then mu st be recharged when r e turning to normal operation. as a result, the wake - up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake - up times. with the recommended 0.1 f and 10 f decoupling cap acitors on reft and refb, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation.
ad9235 data sheet rev. d | page 18 of 40 table 7 . reference configuration summary selected mode sense voltage interna l switch position resulting vref (v) resulting differential span (v p - p) external reference avdd n/a n/a 2 external reference internal fixed reference vref sense 0.5 1.0 programmable reference 0.2 v to vref sense 0.5 (1 + r2/r1) 2 vref (see figure 40 ) internal fixed reference agnd to 0.2 v internal divider 1.0 2.0 digital outputs the ad9235 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digi tal supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performa nce. applications requiring the adc to drive large capacitive loads or large fan - outs may require external buffers or latches. as detailed in table 8 , the data format can be selected for either offset binary or twos complement. tim ing the ad9235 provides latched data outputs with a pipeline delay of seven clock cycles. data outputs are available one propag a- tion delay (t pd ) after the rising edge of the clock signal. refer to figure 2 for a detailed timing dia gram. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9235; these transients can detract from the converters dynamic pe r formance. the lowest typical conversion rate of the ad9235 is 1 msp s. at clock rates below 1 msps, dynamic performance may degrade. voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9235. the input range can be adjusted by varying the refe r- ence voltage applied to the ad9235, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. if the adc is being driven differentially through a transformer, the reference voltage can be used to bias the center ta p (co m mon - mode voltage). internal reference connection a comparator within the ad9235 detects the potential at the sense pin and configures the reference into one of four poss i- ble states, which are summarized in table 7 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 39 ), setting vref to 1 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a r e sistor divider is co n nected as shown in figure 40 , the switch is again set to the sense pin. this puts the reference amplifier in a noninver t ing mode with the vref output def ined as vref = 0.5 (1 + r2 / r1 ) adc core select logic ad9235 vin ? vref sense vin+ refb reft 10 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f 0.5v 02461-039 + + figure 39 . internal reference configuration in all reference configurations, reft and refb drive the a/d conversion core and establish its input span. the input range of the adc always equals twic e the voltage at the reference pin for either an internal or an external reference. 02461-040 sense adc core select logic ad9235 vref vin ? vin+ refb reft 10 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f 0.5v r2 r1 + + figure 40 . programmable reference configuration
data sheet ad9235 rev. d | page 19 of 40 external reference operation the use of an external reference may be necessary to enhance the ga in accuracy of the adc or to improve thermal drift cha r acteristics. when multiple adcs track one another, a single refe r ence (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high precision external reference may also be selected to provide lower gain and offset temperature drift. figure 41 shows the typical drift characteri s- tics of the internal reference in both 1 v and 0.5 v modes. 02461-041 temperature ( c ) 80 ? 40 ? 30 ? 20 ? 10 0 10 20 30 40 50 60 70 vref error (%) 1.2 1.0 0.8 0.6 0.4 0.2 0 vref = 1.0v vref = 0.5v figure 41 . typical vref d rift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equiv a lent 7 k ? load. the internal buffer still generates the positive and negative full - scale references, reft and refb, for the adc core. the input span is always twice the value of the refe r ence voltage; therefore, the external reference must be limited to a maximum o f 1 v. if the internal reference of the ad9235 is used to drive multiple converters to improve gain matching, the loading of the refe r- ence by the other converters must be considered. figure 42 d e picts how the internal reference v oltage is affected by loading. 02461-042 load (ma) 3.0 0 0.5 1.0 1.5 2.0 2.5 error (%) 0.05 0 ? 0.05 ? 0.10 ? 0.15 ? 0.20 ? 0.25 0.5v error (%) 1v error (%) figure 42 . vref accuracy vs. load operational mode sel ection as discussed earlier, the ad9235 can output data in either offset binary or twos complement format. there is also a provision for enablin g or disabling the clock dcs. the mode pin is a mult i- level input that controls the data format and dcs state. the input threshold values and corresponding mode selections are outlined in table 8 . table 8 . mo de selection mode voltage data format duty cycle stabilizer avdd twos complement disabled 2/3 avdd twos complement enabled 1/3 avdd offset binary enabled agnd (default) offset binary disabled the mode pin is internally pulled down to agnd by a 20 k? resistor. tssop evaluation boa rd the ad9235 evaluation board provides the support ci r cuitry required to operate the adc in its various modes and config u- rations. the converter can be driven differentially, through an ad8138 driver or a transformer, or s ingle - ended. separate po w- er pins are provided to isolate the dut from the support ci r- cuitry. each input configuration can be selected by proper co n- nection of various jumpers (refer to the schematics). figure 43 show s the typical bench characterization setup used to evaluate the ac performance of the ad9235. it is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. proper filte r- ing of the input signal, to remove harmonics and lower the int e- grated noise at the input, is also necessary to achieve the spec i- fied noise performance. the auxclk input should be selected in applications requiring the lowest jitter and snr performance, i.e., if u ndersampling characterization. it allows the user to apply a clock input signal that is 4 the target sample rate of the ad9235. a low - jitter, di f ferential divide - by - 4 counter, the mc100lvel33d, provides a 1 clock output that is subsequently returned back to the clk input via jp9. for example, a 260 mhz signal (sinusoid) is d i vided down to a 65 mhz signal for clocking the adc. note that r1 must be removed with the auxclk interface. lower jitter is often achieved with this interface since many rf signal ge nerators display improved phase noise at higher output fr e quencies and the slew rate of the sinusoidal output signal is 4 that of a 1 signal of equal amplitude. complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level.
ad9235 data sheet rev. d | page 20 of 40 lfcsp evaluation boa rd the typical bench setup used to evaluate the ac performance of the ad9235 is similar to the tssop evaluation board co n nections (refer to the schematics for connection detail s). the ad9235 can be driven single - ended or differentially through a transformer. separate power pins are provided to isolate the dut from the support circuitry. each input config u ration can be selected by proper connection of various jumpers (refer to the schematics). an alternative differential analog input path using an ad8351 op amp is included in the layout but is not populated in produ c- tion. designers interested in evaluating the op amp with the adc should remove c15, r12, and r3 and populate the op amp circuit. the passive network between the ad8351 outputs and the ad9235 allows the user to optimize the frequency response of the op amp for the application. data capture and processing 3v ? + 3v ? + 3v ? + 3v ? + refin 10mhz refout hp8644, 2v p-p signal synthesizer hp8644, 2v p-p clock synthesizer band-pass filter s4 xfmr input s1 clock avdd dut avdd gnd gnd dut drvdd dvdd ad9235 tssop evaluation board j1 clock divider 02461-043 figure 43 . tssop evaluation board connections
data sheet ad9235 rev. d | page 21 of 40 r20 1 k ? r17 1 k ? r42 1 k ? r27 5k ? r4 10k ? r3 10k ? d7o d7 d11o d10o d9o d8o d7o d6o d5o d4o d3o d2o d1o d0o jp7 c37 0.1 f dutavdd dutavdd vin+ vin ? otro c36 0.1 f c50 0.1 f u1 jp22 jp23 jp13 avdd dutclk wht tp6 wht tp17 dutdrvdd wht tp5 ad9235 d0 d1 d2 d4 d7 d11 otr avdd sense pdwn refb vin+ vin ? avdd dgnd drvdd d5 mode clk d3 d6 d8 d9 d10 agnd vref reft agnd sheet 3 rp4 22 ? 4 c1 10 f 10v c20 10 f 10v c34 0.1 f c35 0.1 f c21 10 f 10v c57 0.1 f c22 10 f 10v c40 0.001 f c33 0.1 f c32 0.1 f c39 0.001 f 5 7 8 3 4 14 5 6 2 9 10 11 12 23 24 1 28 27 26 25 22 21 20 19 18 17 16 15 13 c38 0.1 f c23 10 f 10v c41 0.001 f jp25 jp24 jp6 jp1 jp2 avdd jp12 agnd dutavddin c59 0.1 f tp2 red dutavdd c58 22 f 25v tb1 2 fbead l1 2 1 tb1 3 avddin c52 0.1 f tp1 red avdd c47 22 f 25v tb1 1 fbead l2 2 1 jp11 agnd drvddin c53 0.1 f tp3 red dutdrvdd c48 22 f 25v tb1 5 fbead l3 2 1 tb1 4 dvddin c14 0.1 f tp4 red dvdd c6 22 f 25v tb1 6 tp11 blk tp12 blk tp13 blk tp14 blk tp9 blk tp10 blk tp15 blk tp16 blk fbead l4 2 1 d6o d6 rp4 22 ? 3 6 d5o d5 rp4 22 ? 2 7 d4o d4 rp4 22 ? 1 8 d3o d3 rp3 22 ? 4 5 d2o d2 rp3 22 ? 3 6 d1o d1 rp3 22 ? 2 7 d0o d0 rp3 22 ? 1 8 otro otr rp6 22 ? 4 5 rp6 22 ? 3 6 rp6 22 ? 2 7 rp6 22 ? 1 8 d11o d11 rp5 22 ? 4 5 d10o d10 rp5 22 ? 3 6 d9o d9 rp5 22 ? 2 7 d8o d8 rp5 22 ? 1 8 02461-044 + + + + + + + + + figure 44 . tssop evaluation board schematic, dut
ad9235 data sheet rev. d | page 22 of 40 wht tp7 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 5 7 3 1 hdr40ram j1 header right angle male no ejectors otr c11 0.1 f d11 d10 d9 d8 dutclk u7 74vhc541 18 2 11 12 13 14 15 16 17 20 10 19 1 9 8 7 6 5 4 3 avdd avdd; 14 avdd; 7 2 1 1 2 5 6 avdd avdd avdd avdd jp4 d2 d1 auxclk mc100lvel33d u3 6 5 7 8 4 3 2 1 c13 0.1 f r1 49. 9 ? avdd 1n5712 a2 a3 a4 a5 a6 a7 a8 g1 g2 gnd vcc y2 y3 y4 y5 y6 y7 y8 a1 y1 74vhc04 u8 74vhc04 u8 1n5712 cw nc ina inb incom vcc out vee ref u8 decoupling r19 500 ? r2 10 ? r18 500 ? r7 22 ? r11 49.9 ? r15 90 ? r13 113 ? r26 10 k ? r25 10 k ? c26 0.1 f c28 10 f 10v c24 0.1 f c5 10 f 10v d5 c12 0.1 f d3 d2 d1 d0 u6 74vhc541 18 2 11 12 13 14 15 16 17 20 10 19 1 9 8 7 6 5 4 3 2 1 a2 a3 a4 a5 a6 a7 a8 g1 g2 gnd vcc y2 y3 y4 y5 y6 y7 y8 a1 y1 c4 10f 10v d4 d6 d7 dvdd rp2 22 ? 8 9 rp2 22 ? 7 10 rp2 22 ? 6 11 rp2 22 ? 5 12 rp2 22 ? 4 13 rp2 22 ? 3 14 rp2 22 ? 2 15 rp2 22 ? 1 16 rp2 22 ? 8 9 rp2 22 ? 7 10 rp2 22? 6 11 rp2 22 ? 5 12 rp2 22 ? 4 13 rp2 22 ? 3 14 rp2 22 ? 2 15 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 daclk dotr dd11 dd10 dd9 dd8 rp2 22 ? 1 16 t2 t1?1t 6 1 2 5 2 1 3 4 s5 clock 1 2 s1 r14 90? r12 113 ? c27 0.1f avdd u9 decoupling c8 10f 10v c10 0.1f jp9 3 4 74vhc04 u8 jp3 13 12 74vhc04 u8 11 10 u8 9 8 74vhc04 u8 02461-045 r9 22? + + + figure 45 . tssop evaluation board schematic, clock inputs and output buffering
data sheet ad9235 rev. d | page 23 of 40 r32 1k? r23 1k? r16 1k? c18 0.1f c2 val c9 0.33f s2 2 1 2 1 avdd c7 0.1f r5 49.9? c8 0.1f c16 0.1f c25 0.33f r37 499? r6 40? r10 40? jp8 2 3 1 c15 10f 10v 2 1 c69 0.1f tp8 red jp5 c17 val r8 1k? avdd avdd r41 1k? r33 1k? avdd amp input s4 2 1 xfmr input alt vee r34 523? r35 499? r31 49.9? r36 499? c19 10f 10v 3 6 4 5 2 8 1 ad8138 u2 a b c42 val c45 val t2 t1?1t 6 5 2 1 3 4 s3 2 1 single input jp46 c43 15pf r22 22? vin? jp41 jp43 jp45 c44 15pf r21 22? vin+ jp40 jp42 c44b 02461-046 r24 49.9? +in vee vo? voc vo+ vcc ?in + figure 46 . tssop evaluation board schematic, analog input s dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 c30 0.1 f c31 0.01 f c49 0.1 f c51 0.1 f c54 22pf r28 49.9 ? r29 49.9 ? c55 22pf c56 0.1 f r30 2k ? daclk dd0 dd1 dvdd s6 wht tp18 ad9762 u4 nc2 db10 db19 db8 db7 db6 db5 db4 db3 nc1 db0 db1 db2 sleep reflo refio fsadj comp1 acom ioutb iouta comp2 avdd nc3 dcom dvdd clock msb - db11 02461-047 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 c29 0.1 f c46 0.01 f figure 47 . tssop evaluation board schematic, optional dac
ad9235 data sheet rev. d | page 24 of 40 02461-048 figure 48 . tssop evaluation board layout, primary side
data sheet ad9235 rev. d | page 25 of 40 02461-049 figure 49 . tssop evaluation board layout, secondary sid e
ad9235 data sheet rev. d | page 26 of 40 02461-050 figure 50 . tssop evaluation board layout, ground plane
data sheet ad9235 rev. d | page 27 of 40 _ 02461-051 figure 51 . tssop evaluation board power plane
ad9235 data sheet rev. d | page 28 of 40 02461-052 figure 52 . tssop evaluation board layout, primary silkscreen
data sheet ad9235 rev. d | page 29 of 40 02461-053 figure 53 . tssop evaluation board layout, secondary silkscreen
ad9235 data sheet rev. d | page 30 of 40 1 2 3 4 5 6 p13 p14 xfrin1 nc r single ended r18 25? extref 1v max e1 r1 10k? gnd avdd gnd c22 10f gnd c8 0.1f p5 p6 p11 p1 p3 p4 2 2 mode refb reft avdd agnd vin+ agnd avdd vin? ad9235 u4 vref sense mode d11 otr d10 d9 d8 drvdd dgnd d7 d5 d6 d4 d3 d2 (lsb) drvdd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d6x d5x d4x d2x d3x d1x d0x (msb) overrange bit avdd gnd drvdd vdl gnd vamp p2 h1 mthole6 3.0v 2.5v 5.0v rp1 220 ? r8 1k? clk avdd r15 33? gnd gnd or l1 for filter gnd avdd r36 1k? r26 1k? gnd avdd avdd gnd gnd vin+ vin? c19 15pf c21 10pf r2 xx r10 36? r42 0? r12 0? x out x out ampin gnd x out b x out b r3 0? r11 36? c26 10pf e 45 c16 0.1f c6 0.1f gnd amp c15 0.1f l1 10nh gnd pri sec gnd c18 0.1f j1 r7 1k? 2.5v sense pin solderable jumper e to a external voltage divider e to b internal 1v reference (default) e to c external reference e to d internal 0.5v reference mode pin solderable jumper 5 to 1 twos complement/dcs off 5 to 2 twos complement/dcs off 5 to 3 offset binary/dcs on 5 to 4 offset binary/dcs off 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 dnc clk dnc dnc pdwn dnc d0 d1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 drx d13x d12x d10x d11x d9x d8x rp2 220 ? h2 mthole6 h3 mthole6 h4 mthole6 gnd 3 r6 1k? 4 1 r5 1k? gnd avdd gnd d c13 0.10f c e p8 b p9 p10 p7 a c29 10f gnd r9 10k? gnd c12 0.1f gnd c9 0.10f c11 0.1f gnd c7 0.1f r4 33k? avdd r13 1k? r25 1k? gnd gnd c23 10pf c5 0.1f ampinb t1 adt 1?1 wt 1 5 2 6 4 3 x frin gnd pri sec optional xfr t2 ft c1?1?13 1 2 5 4 3 ct ct r3, r17, r18 only one should be on board at a time 02461-054 + d7x figure 54 . lfcsp evaluation board schematic, analog inputs and dut
data sheet ad9235 rev. d | page 31 of 40 drx d13x gnd d2x d1x gnd d0x d11x d12x drvdd d10x d9x gnd d8x d7x d5x d6x gnd d4x d3x drvdd 2clk 2db 2d7 gnd 2d6 2d5 v cc 1d2 1d1 1clk 2d4 2d3 gnd 2d2 2d1 1d7 1d6 1d5 1d8 gnd v cc 1d4 1d3 gnd 2qb 2q7 gnd 2q6 2q5 v cc 1q2 1q1 1oe 2q4 2q3 gnd 2q2 2q1 1q8 1q7 1q6 1q5 gnd v cc 1q4 1q3 gnd 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 in out clkat/dac 1 74lvth162374 u1 clklat/dac gnd gnd gnd gnd gnd gnd dry msb lsb 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 gnd dr msb gnd gnd header 40 dry drvdd drvdd gnd ampin ampinb gnd gnd gnd vamp c27 0.1f c28 0.1f c35 0.10f c17 0.1f r16 0? r14 25? r40 10k? pwdn rgp1 inhi inlo rpg2 r41 10k? r35 25? r34 1.2k? amp in amp ad8351 u3 power down use r40 or r41 c44 0.1f comm oplo oph1 vpos vocm 5 4 2 3 1 6 9 10 r33 25? r41 10k? r19 50? vamp vamp r38 1k? r39 1k? gnd gnd c24 10f gnd c45 0.1f gnd r17 0? 7 gnd 8 02461-055 2oe + figure 55 . lfcsp evaluation board sche matic, digital path
ad9235 data sheet rev. d | page 32 of 40 clock timing adjustments for a buffered encode use r28 f or a direct encode use r27 gnd encx enc r32 1k ? r37 25 ? r23 0 ? r22 0 ? rx dnp r28 0 ? e50 e51 enc clk vdl gnd gnd vdl gnd pwr c43 0.1 f r31 1k ? r30 1k ? r29 50 ? j2 gnd vdl 1y encx 1 2 1b 1a dr schematic shows two gate delay setup for one delay remove r22 and r37 and attach rx (rx = 0 ? ) c49 0.001 f c48 0.001 f c47 0.1 f c1 0.1 f c39 0.001 f c38 0.001 f c36 0.1 f c34 0.1 f c31 0.1 f c30 0.001 f c2 22 f drvdd gnd c37 0.1 f c40 0.001 f c20 10 f vdl gnd c46 10 f vamp gnd gnd c14 0.001 f c41 0.1 f c33 0.1 f avdd digital bypassing analog bypassing dut bypassing latch bypassing c32 0.001 f c25 10 f c3 10 f c4 10 f c10 22 f 2y 4 5 2b 2a 3y 9 10 3b 3a 4y 12 13 3 6 7 8 11 14 4b 4a clkat/dac r20 1k ? e52 e53 vdl gnd r21 1k ? e31 e35 vdl gnd r24 1k ? e43 e44 vdl gnd r27 0 ? gnd vdl drvdd avdd 02461-056 encode gnd 74vcx86 + + + + + + figure 56 . lfcsp evaluation board schematic, clock input
data sheet ad9235 rev. d | page 33 of 40 02461-057 figure 57 . lfcsp evaluation board layout, primary side 02461-058 figure 58 . lfcsp evaluation board l ayout, secondary side 02461-059 figure 59 . lfcsp evaluation board layout, ground plane 02461-060 figure 60 . lfcsp evaluation board layout, power plane
ad9235 data sheet rev. d | page 34 of 40 02461-061 figure 61 . lfcsp evaluation board layo ut, primary silkscreen 02461-062 figure 62 . lfcsp evaluation board layout, secondary silkscreen
data sheet ad9235 rev. d | page 35 of 40 table 9 . lfcsp evaluation board bill of materials (bom) item qty. omit 1 reference designator device package value recommended ve n dor/ part number supplied by adi 1 18 c1, c5, c7, c8, c9, c11, c12, c13, c15, c16, c31, c33, c34, c36, c37, c41, c43, c47 chip capacitor 0603 0.1 f 8 c6, c18, c27, c17, c28, c35, c45, c44 2 8 c2, c3, c4, c10, c20, c22, c25, c29 tantalum capacitor tajd 10 f 2 c46, c24 3 8 c14, c30, c32, c38, c39, c40, c48, c49 chip capacitor 0603 0.001 f 4 3 c19, c21, c23 chip capacitor 0603 10 pf 5 1 c26 chip capacitor 0603 10 pf 6 9 e31, e35, e43, e44, e50, e 51, e52, e53 header ehole jumper blocks 2 e1, e45 7 2 j1, j2 sma connector/50 ? sma 8 1 l1 inductor 0603 10 nh coilcraft/ 0603cs - 10nxgbu 9 1 p2 terminal block tb6 wieland/25.602.2653.0, z5 - 530- 0625 -0 10 1 p12 header dual 20 - pin rt a n gle header40 digi - key s2131- 20- nd 11 5 r3, r12, r23, r28, rx chip r esistor 0603 0 ? 6 r37, r22, r42, r16, r17, r27 12 2 r4, r15 chip resistor 0603 33 ? 13 14 r5, r6, r7, r8, r13, r20, r21, r24, r25, r26, r30, r31, r32, r36 chip resistor 0603 1 k ? 14 2 r10, r11 chip resistor 0603 36 ? 15 1 r29 ch ip resistor 0603 50 ? 1 r19 16 2 rp1, rp2 resistor pack r_742 220 ? digi - key cts/742c163220jtr 17 1 t1 adt1 - 1wt awt1 - 1t mini - circuits 18 1 u1 74lvth162374 cmos register tssop -48 19 1 u4 ad9235bcp adc (dut) lfcsp -32 analog devices, inc. x 20 1 u5 74vcx86m soic -14 fairchild 21 1 pcb ad92xxbcp/pcb pcb analog devices, inc. x 22 1 u3 ad8351 op amp msop -8 analog devices, inc. x 23 1 t2 macom transformer etc1 -1 -13 1 - 1 tx m / a - com/etc1 -1 -13 24 5 r9, r1, r2, r38, r39 chip re sistor 0603 select 25 3 r18, r14, r35 chip resistor 0603 25 ? 26 2 r40, r41 chip resistor 0603 10 k ? 27 1 r34 chip resistor 1.2 k ? 28 1 r33 chip resistor 100 ? total 82 34 1 these items are included in the pcb design but are omitted at assembly.
ad9235 data sheet rev. d | page 36 of 40 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 63 . 28 - lead thin shrink small outline pack age [tssop] (ru - 28) dimensions shown in millimeters compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 64 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 5 mm body, very very thin quad (cp - 32 - 7) dimensions shown in millimeters
data sheet ad9235 rev. d | page 37 of 40 ordering guide model 1 , 2 temperature range package description package option ad9235bru -20 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235brurl7 -20 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bruz -20 C 40c to +85c 28- lead t hin shrink small outline package (tssop) ru -28 ad9235bruzrl7 - 20 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bru -40 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235brurl7 -40 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bruz -40 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bruzrl7 - 40 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bru -65 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235brurl7 -65 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bruz -65 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bruzrl7 - 6 5 C 40c to +85c 28- lead thin shrink small outline package (tssop) ru -28 ad9235bcpz - 20 C 40c to +85c 32 - lead lead frame chip scale package (lfcsp_wq) cp - 32 - 7 ad9235bcpzrl7 -20 C 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-7 ad92 35bcpz -40 C 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-7 ad9235bcpzrl7 -40 C 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-7 ad9235bcpz -65 C 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-7 ad9235bcpzrl7 -65 C 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-7 1 z = rohs compliant p art. 2 it is recommended that the exposed paddle be soldered to the ground plane. there is an increased reliabili ty of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board.
ad9235 data sheet rev. d | page 38 of 40 notes
data sheet ad9235 rev. d | page 39 of 40 notes
ad9235 data sheet rev. d | page 40 of 40 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02461-0-10/12(d)

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